1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, more particularly to a method of forming a plurality of MOS transistors on a substrate wherein different source voltages are supplied to the MOS transistors respectively.
2. Description of the Related Art
A semiconductor integrated circuit device in which transistors whose gate electrodes are made of polysilicon and transistors whose gate electrodes are made of metal are formed on a semiconductor substrate has been in a practical use instead of the conventional semiconductor device using only transistors whose gate electrodes are made of polysilicon, because the polysilicon shows high resistivity which is load for fast operation.
Since an I/O section of such the semiconductor device requires stable drive, it has relatively long gate length, a thick gate insulation film, and is driven by a relatively high voltage. A gate electrode of the I/O section is made of polysilicon.
Another section of the above described semiconductor device is a core section which performs substantial operation of the circuit, such as calculation. Since the core section requires fast operation, it has a metal gate electrode, and is driven by a relatively low voltage. Fine design rule is applied to the core section, that is, the thickness of a gate insulation film is thinner than that of the I/O section.
Unexamined Japanese Patent Application KOKAI Publication No. H4-162771 discloses a semiconductor integrated circuit device whose structure is similar to the above. According to the application, a gate insulation film (for I/O section) having a first thickness is formed by thermal oxidization, and another gate insulation film (for core section) is formed by thermal oxidization. The second oxidization for forming the gate insulation film of the core section further oxidizes the gate insulation film of the I/O section, thus, it becomes thicker. Accordingly, it is difficult to form desired gate insulation film of the I/O section.
Unexamined Japanese Patent Application KOKAI Publication No. S58-124268 discloses an integrated circuit device in which a transistor having a polysilicon gate electrode and a transistor having a metal gate electrode are formed on a semiconductor substrate. According to the disclosed technique, a gate insulation film beneath the polysilicon gate electrode and another gate insulation film beneath the metal gate electrode are formed simultaneously, therefore, they have the same thickness.
Unexamined Japanese Patent Application KOKAI Publication No. S58-61645 discloses a master slice integrated circuit device. The disclosed technique realizes an integrated circuit device having less occupied area with well-regulated arrangement by sharing a source/drain region of a drive MOS transistor and a source/drain region of a load MOS transistor. However, the application does not have any description regarding to gate insulation films for the transistors.
The present invention has been made in consideration of the above, it is an object of the present invention to provide a method of manufacturing a reliable semiconductor device in which a plurality of transistors whose gate electrode insulation films have different thickness.
To achieve the above object, a method according to the present invention is a method of manufacturing a semiconductor device comprises:
forming a section separator region in a semiconductor substrate to separate the semiconductor substrate into a first region and a second region;
forming a first insulation film at the first region on the semiconductor substrate
forming a first gate electrode material layer on the first insulation film;
forming a second insulation film whose thickness differs from the thickness of the first insulation film over the exposed surface after the first gate electrode material layer is formed;
forming a second gate electrode material layer on the second gate insulation film
removing the second gate electrode material layer at the first region after the second gate electrode material layer is formed;
forming a first gate electrode with the first gate electrode material layer at the first region after the second gate electrode material layer is removed, while forming a second gate electrode with the second gate electrode material layer at the second region;
removing second insulation film remaining on the first gate electrode after the first and second gate electrodes are formed;
forming first source/drain regions at the first region, and forming second source/drain regions at the second region, after the second insulation film is removed; and
etching the first and second insulation films with masking by the first and second gate electrodes to form a first and second gate insulation films, after the first and second source/drain regions are formed.
The method may further comprises:
forming a protection film on the first gate electrode material layer;
forming a second insulation film at the second region after the protection film is formed; and
forming a second gate electrode material layer over an exposed surface including surfaces of the protection film and the second insulation film, after the second insulation film is formed.
The removing steps may include polishing the second gate electrode material layer on the protection film which acts as a stopper.
The protection film may be made of silicon nitride.
In this case, the first and second source/drain regions may have predetermined concentration;
side walls of the first and second gate electrodes may be formed after the source/drain regions are formed;
third and fourth source/drain regions whose concentration differs from the predetermined concentration of the first and second source/drain regions may be formed so as to connect to the first and second source/drain regions respectively, after the side walls are formed; and
the forming gate insulation film may include etching the first and second gate insulation films with masking by the first and second gate electrodes and the side walls.
The second gate electrode material layer may include a refractory metal or refractory silicide.
In this case, the method may further comprise forming a barrier metal between the second gate electrode material layer including the refractory metal or refractory silicide and the second gate electrode insulation film.
According to the above method, the pre-formation treatment is carried out while the first gate electrode material layer to be a first gate electrode has been formed on the first oxide film at the first region. Therefore, the first oxide film is not damaged by the preformation treatment. Further, the first gate electrode material layer acts as a protection film while forming the second oxide film for the second region by the thermal oxidization. Therefore, no additional oxide film is formed on the first oxide film.